Field of the Invention
The present invention relates to a configuration and method for checking an address generator. The address generator is part of a test apparatus that is in turn part of an integrated circuit. The test apparatus has a set of first switching devices and a set of second switching devices. The address generator has a given number of address outputs which can be connected through the set of first switching devices to lines of an address bus in the integrated circuit in order to output first address values, generated in the address generator, onto the address bus of the integrated circuit. The test apparatus has a memory apparatus with memory elements whose number is equal to the given number of address outputs of the address generator. The memory apparatus can be supplied with an external address signal in order to store second address values, and the second address values stored in the memory apparatus can be output from the memory elements in the memory apparatus onto the lines of the address bus in the integrated circuit through the set of second switching devices.
The operation of integrated circuits is known to need testing both during the development phase and during and after the manufacturing process. Such function tests can, depending on the type of integrated circuit to be tested, require a very long period of time to perform them. A long period of time slows down the number of circuits which can be tested per unit time, however, which then affects the productivity of the manufacturing process and results in higher costs. It is possible to increase the number of circuits that can be tested per unit time by increasing the number of test machines used for performing the tests. However, this also increases the costs in the form of higher (overall) purchase costs for the test machines.
Against this background, however, some types of integrated circuits are configured such that (at least in theory) parts of them can be tested in parallel with one another at the same time, although no provision at all (or at least not in this scope) is made for such contemporaneous parallel operation for these circuits in normal mode. Such circuits are, in particular, microprocessors (or at least subdivisions of microprocessors), semiconductor memories and circuits with integrated memory arrays (“embedded DRAMs”). Particularly in the field of integrated semiconductor memories, consideration was given even many years ago to how their test time could be reduced without any loss of test depth. By way of example, Published, European Patent Application EP 0 186 040 A1, corresponding to U.S. Pat. No. 4,742,490, proposed almost 20 years ago, testing the operation of integrated semiconductor memories in a manner such that a special test mode is used to test memory cells disposed in different memory cell arrays at the same time and in parallel with one another. Since then, the nature of these “parallel tests” has been continually refined.
Today, there are integrated semiconductor memories of the DRAM type, for example, in which values of address signals which would actually need to be applied to the semiconductor memory from the outside (normal mode) are generated internally in the chip by a dedicated address generator, whose operation may even be programmable, and the values are then applied to the lines of address buses. However, this disadvantageously results in that, before such an address generator is used for the purpose of testing the semiconductor memory, the address generator itself should first be checked for correct operation. In this case, new problems arise, however: minute needle tips, “picoprobes”, would need to be used to ascertain the profile of the address signals which are on the lines in the address bus. This ranges from very difficult to impossible, however: first, the narrowness of the lines results in that there is a problem in fitting such needle tips precisely on the interconnects. Second, the interconnects are often totally inaccessible, at least without special analytical processes such as etching away layers etc., which then also in turn results in that the semiconductor memory is destroyed, because the interconnects are situated beneath a passivation layer or even beneath a number of other wiring planes. The latter is so particularly in the case of such integrated circuits as have “embedded memory” regions. These are known to be circuits which perform any, usually digital, functions and which, in order to perform these functions, need to revert to values that are stored “anywhere” (one example which may be used for such stored information is “ignition under the control of characteristic maps” in electronic ignitions in motor vehicles, implemented using integrated circuits). This “anywhere” is today frequently implemented on the same integrated circuit as the actual circuit itself, namely in a dedicated memory area.